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dpa-switch ? dc-dc forward converter design guide application note an-31 introduction the single-ended forward converter topology is usually the best solution for dc-dc applications in industrial controls, telecom central of?ce equipment, digital feature phones, and systems that use distributed power architectures. the feature set of dpa-switch offers the following advantages in dc-dc single-ended forward converter designs: ? low component count ? high ef?ciency (typically >91% with synchronous recti?cation) ? built in soft-start to minimize stress and overshoot ? built in accurate line under-voltage detection ? built-in accurate line overvoltage shutdown protection ? built in adjustable current limit ? built-in overload and open loop fault protection ? built-in thermal shutdown ? programmable duty cycle reduction to limit duty cycle excursion at high line and transient load conditions ? very good light-load ef?ciency ? selectable 300 khz or 400 khz operation ? lossless integrated cycle-by-cycle current limit the example circuits in this design guide illustrate the use of these and other features of dpa-switch . scope this document gives guidance for the design of a single- ended forward converter with dpa-switch in applications that require a single output voltage. it is intended for systems engineers and circuit designers who wish to become familiar with the capabilities and requirements of dpa-switch in dc-dc applications. this application note provides background material that will assist users of the dpa-switch dc-dc forward converter design utility that is included in the software design tool, pi expert . subsequent application notes will provide comprehensive procedures for designs of greater complexity. designers are advised to check power integrations? website at www.powerint.com for the latest application information and design tools. u1 d l s f c dc input v o + C r fc c bypass r uvlo c clamp drain clamp snubber power transformer output inductor bias voltage output capacitor input return pi-2873-062204 feedback circuit control control dp a-switch tl431 with frequency compensation c fc + + figure 1. typical con?guration of dpa-swtich in a single-ended dc-dc forward converter with one output. july 2004
an-31 c 7/04 2 description symbol min typ max units comment input input voltage input voltage uv turn on input voltage uv turn off input voltage ov turn on input voltage ov turn off v in 36 29 48 75 36 72 90 vdc vdc vdc vdc vdc typical operational range output output voltage output ripple and noise output current v out v ripple i out 4.8 0 5.00 50 5.2 6.00 v mv a 4% 20 mhz bandwidth line regulation load regulation 0.2 0.5 % % transient response peak deviation transient response recovery 3 200 % of v out s 50-75% load step, 100 ma/ s 48 vdc input to 1% of ?nal output voltage, 50-75% load step, 48 vdc input total output power continuous output power p out 30 w ef?ciency low-cost design enhanced (non-sync rect.) synchronous recti?ed design cost enhanced syncrect 84 87 91 % % % measured at p out (30 w), 25 c, 48 vdc input environmental input-output isolation voltage ambient temperature t amb 1500 -40 85 vdc c free convection, sea level figure 1 shows a typical implementation of dpa-switch in a power supply with a single regulated output. this design guide discusses considerations for selection of components for a practical implementation of the circuit in figure 1. it also addresses options and tradeoffs in cost, ef?ciency and complexity that include the substitution of synchronous recti?ers and alternative generation of the bias voltage. system requirements the design begins with an evaluation of the requirements. table 1 gives the speci?cations for the example converters described here, that have been constructed and evaluated as engineering prototypes. variants of the basic design achieve higher ef?ciencies with minor increases in complexity. input voltage range the actual input voltage range required for operation of the converter is greater than that indicated by the speci?cation. the speci?cation requires the converter to operate and to deliver full performance at a minimum input of 36 v. therefore, the designer must guarantee that the converter becomes active and fully functional at a voltage that is lower than the minimum. tolerance variations of the line undervoltage threshold of dpa-switch with prudent design margin put the practical minimum operating voltage closer to 30 v. similarly, the converter must be designed to operate at voltages higher than the maximum speci?ed input. the actual input voltage range should be considered to be from about 30 v to 90 v for the typical nominal input voltage of 48 vdc. output characteristics the output voltage can be maintained to 4% over the range of line, load and operational temperature range with an ordinary feedback circuit that uses a tl431 regulator. transient response is controlled with proper frequency compensation. the design of the feedback network with guidance for selection of component values is addressed in a separate section. ripple and noise are strongly in?uenced by the size of the output inductor and the choice of output capacitors. these topics are discussed more thoroughly later in this document. table 1. typical speci?cations for a single output dc-dc converter.
an-31 c 7/04 3 figure 2. methods for generation of bias voltage. u2 d l s x f c control control dp a-switch pi-3468-042303 + (a) dc input derived u2 d l s x f c control control dp a-switch pi-3469-042303 + (b) transformer bias (unregulated) u2 d l s x f c control control dp a-switch pi-3470-042303 + (c) output coupled inductor bias u2 d l s x f c control control dp a-switch pi-3471-042303 + (d) transformer bias (regulated) output recti?ers output recti?cation may be accomplished with discrete schottky diodes for lowest cost or synchronous recti?ers for highest ef?ciency. this document discusses synchronous recti?cation in greater detail in a separate section. ultra-fast pn junction diodes are not suitable at dpa-switch operating frequencies.
an-31 c 7/04 4 ef?ciency designing a dc-dc converter with dpa-switch involves several engineering tradeoffs that weigh ef?ciency against cost and complexity. the circuit con?guration in figure 1 achieves ef?ciencies greater than 85% over the range of input voltage at medium loads. in typical applications without synchronous rectifcation, approximately 25% of the total power loss will be in the dpa-switch (see dpa-switch data sheet), 40% in the output recti?ers, and 30% in the magnetic devices. the remainder is distributed among other devices and circuit traces. higher ef?ciencies of approximately 91% can be obtained when schottky recti?ers are replaced by synchronous recti?ers, allowing lower voltage drops. the ef?ciency can be raised even higher with the use of the next larger device in the dpa-switch family that has lower r ds(on) . further increases in device size may not improve the ef?ciency due to increased device switching losses. losses in the magnetic devices can be reduced by using larger cores and by switching at 300 khz instead of 400 khz. all these alternatives have compromises in size, cost and complexity that the designer must evaluate. temperature dc-dc converters usually must operate over an extended range of temperature that goes beyond the limits for ordinary consumer electronics. designers should be aware that the characteristics of passive components are likely to change signi?cantly with temperature. attention to these effects to choose suitable components can prevent unexpected and undesirable behavior. designers must pay particular attention to the selection of the output capacitors and the components in the feedback circuit to guarantee speci?ed performance throughout the temperature range. the details are addressed later in the sections on output capacitor selection and feedback design. bias voltage there are four ways to generate the bias voltage required for operation of dpa-switch : (a) dc input derived (b) transformer bias (unregulated) (c) output coupled inductor winding (d) transformer bias (regulated) figure 2 illustrates the four alternatives. each one must provide a minimum of 8 v at the collector of the optocoupler under worst case operating conditions (minimum input voltage and minimum load). the lowest bias voltage under typical conditions should be 12 v. the output coupled inductor and the regulated transformer bias techniques give the highest ef?ciency of the four solutions because the voltage across the optocoupler is controlled. this is countered by increased complexity. optocoupler dissipation can be signi?cant and should be veri?ed. maximum optocoupler phototransistor current is equal to the maximum control pin current (i c(skip) ) for the selected dpa-switch . maximum dissipation therefore occurs at the highest bias voltage (highest input voltage for (a) and (b)) and minimum load. table 2 provides a comparison of complexity vs performance for all the solutions. a) the dc input derived bias is the simplest of the three solutions. it uses a zener diode between the positive dc input and the collector of the phototransistor of the optocoupler to reduce the maximum collector-to-emitter voltage, and more importantly, to limit the dissipation in the optocoupler. the penalty for simplicity is a reduction in ef?ciency that can be signi?cant at high input voltages. this alternative is best for industrial applications where the input voltage is low (18 v to 36 v). the input voltage in industrial applications is usually low enough to eliminate the zener diode because the breakdown voltages for standard optocouplers can be as high as 70 v. designers must check the maximum power dissipation in the optocoupler in either case. b) the transformer bias (unregulated) is created from a winding on the power transformer. the forward bias winding should be connected to the recti?er in a polarity such that it conducts when the dpa-switch is on. since the bias voltage is proportional to the input voltage, ef?ciency is reduced at high input voltages, but the effect is less than with the direct connection to the input. again, the designer needs to check the power dissipation in the optocoupler at the maximum bias voltage. for this bias type, worst case is minimum output load and high input voltage. flyback bias windings are not recommended for dpa-switch applications since they will affect the transformer reset. c) output coupled inductor bias uses a winding on the output inductor to develop the bias voltage. this technique provides a well regulated bias voltage when the converter operates in the continuous conduction mode. regulation is accomplished by phasing the winding such that the bias voltage is proportional to the output voltage by transformer action when the dpa-switch turns off. the penalty for the higher ef?ciency is the cost and complexity of a custom output inductor. the bias voltage can be adjusted by modifying turns ratio, bias capacitor size and minimum load on the main output. the designer should verify a minimum bias voltage of 8 v at minimum load and maximum input voltage. d) the transformer bias (regulated) solution peforms the same function as the output coupled inductor bias (c). the bias voltage regulation is not quite as good as with the output coupled inductor bias. however, the solution does provide a reasonably constant bias voltage over a variety
an-31 c 7/04 5 table 2. bias voltage solution comparison. of input voltage and output load conditions. this solution works best if the independent inductor is maintained in the continuous conduction mode. the solution can be implemented with a low current, low cost (off-the-shelf) inductor, but the inductance value will be high enough to ensure continuous conduction mode over the majority of operating conditions. transformer design the power transformer is critical to the success of the converter design. requirements for ef?ciency, component height and footprint will determine the details of construction. system engineers and circuit designers may choose to specify the electrical parameters and mechanical limits, and delegate the construction details to a supplier of custom transformers. use the pi expert design tool to determine the proper parameters. this section gives guidance for speci?cation of the transformer. turns ratio the most important parameter for the power transformer is the primary-to-secondary turns ratio. it must be low enough to provide the regulated output voltage at the minimum input voltage. determine the minimum input voltage from the system speci?cation and the tolerance of the line under-voltage lockout circuit. whereas the minimum input voltage may be speci?ed at 36 v, worst case tolerances of the under-voltage circuit are likely to allow the dpa-switch to operate at an input as low as 29 v. from this voltage, subtract the estimated drain-to-source voltage of dpa-switch at the maximum load. reduce it further by an estimate of the voltage drop from the high frequency ac resistance of the transformer windings at full load. multiply the result by the maximum guaranteed duty ratio and divide by the sum of the output voltage and the drop on the output recti?er at full load. the duty ratio can be greater than 50% because dpa-switch uses a voltage mode control. the quotient is the upper limit for the turns ratio. core and copper the actual number of turns for the transformer will depend on the dimensions of the particular core. the core material should be low loss at the dpa-switch operating frequencies. technical data on properties of ferrite cores are available from several suppliers. see references [1], [2] and [3]. skin effect and proximity effect will set a practical limit for wire size. foil windings become attractive when the output current is higher than about 6 a. thermal considerations often dominate selection of the core. the selection of the core is a complex trade-off between winding area, core cross-section and ratio of core surface area to core volume. these parameters determine the power loss as well as the thermal resistance of the transformer. a small core may meet the requirements in every respect except temperature rise, forcing the use of a larger core. the only practical way to check temperature rise is with bench evaluation of a prototype. temperature must be measured at the hottest spot in the transformer, which is usually next to the center of the core under the windings. wire temperatures above 110 c need special considerations and ul class f materials. other practical considerations minimize the number of turns within the limits of other constraints. resistive losses depend on the length of the wire. maximize the amount of copper (wire) that can be ?tted within the winding window. leakage inductance must be kept low to reduce losses associated with clamp components. this is best accomplished with a split primary construction that has the secondary between the layers of the primary winding. also, all transformers should have no air gap. bias type input voltage range (v) ef?ciency cost complexity comment dc input derived bias 18 to 36 ? ? recommended for 18 to 36 v only transfer bias (unregulated) 36 to 72 ? ? recommended for low-cost design output coupled inductor bias 36 to 72 ? ? only recommended if supply already requires coupled output inductor transformer bias (regulated) 36 to 72 ? ? recommended for high ef?ciency designs
an-31 c 7/04 6 if the transformer has a winding for the bias voltage, be sure that it has enough turns to maintain a minimum of 8 v bias at the lowest input voltage. perform bench veri?cation to con?rm that the converter shuts off at low input voltages by virtue of the under-voltage lockout circuit, and not because the bias voltage is too low. with the actual number of turns on the transformer, verify that the duty ratio to regulate the output at the minimum input voltage is less than the minimum dc max speci?ed for dpa-switch. the ac ?ux density contributes to the core losses. for this reason the ac ?ux density should be maintained in the range between 1000 and 1500 gauss (0.1 to 0.15 tesla). output inductor for a single output application with no bias winding, the inductor can be a standard off-the-shelf component. inductors with multiple windings are typically custom designs. the inductor value is determined chie?y by the amount of current ripple that the designer is willing to tolerate. higher ripple current will allow an inductor that is smaller both electrically and physically. the consequence of higher ripple current is the requirement for more output capacitance with lower equivalent series resistance (esr) to meet the speci?cation for output ripple. higher current ripple in the inductor also translates to higher peak current in the dpa-switch for a given output power. it also leads to generally greater loss and lower ef?ciency because the rms value of all the currents will be higher. a convenient design parameter for selection of the inductor is k ? i , de?ned as the ratio of the peak-to-peak ripple current to the average current in the inductor. smaller k ? i corresponds to 90% 86% 88% 35 40 45 50 55 60 65 70 75 dc input voltage efficiency (%) pi-2886-04220 4 80% 82% 84% dpa42 4 dpa42 5 dpa42 6 figure 3. ef?ciency of the low cost ep-21 prototype with different devices in the dpa-switch family (synchronous recti?cation would improve ef?ciency). lower ripple and a larger inductor. recommended values for k ? i are between 15 and 20 percent. the choice of k ? i involves a trade-off between the size of the inductor, the number and type of output capacitors, ef?ciency, and cost. higher values of k ? i are not recommended, as these higher ripple currents increase both the stress and the ripple voltage on the output capacitor. whether the inductor is standard off-the-shelf or custom, the design should minimize the number of turns to reduce the resistive loss. the construction should also use a low loss core material. with user input, the pi expert design tool computes the inductance, the rms current and the peak stored energy to aid in the selection or speci?cation of the inductor. peak stored energy is a useful parameter to select designs that use a closed toroid core, where magnetic saturation is generally a concern. additional winding for bias voltage if the con?guration in figure 2 (c) is chosen for generation of the bias voltage, choose the number of turns on the bias winding to give 12 v at the optocoupler under nominal conditions. compute the required number of turns from the lowest regulated output voltage and the highest forward voltage drops for the output recti?er and the bias recti?er. check the bias voltage at minimum load, maximum line, and add a preload if necessary to maintain the bias voltage at 8 v minimum. it may also be necessary to increase the bias winding turns to meet the minimum voltage requirement with a reasonably small pre-load. dpa-switch selection the ?rst criterion for the selection of the dpa-switch is peak current capability. from the turns ratio of the transformer and the peak current in the output inductor, estimate the peak current in the primary of the transformer. the magnetization current of the transformer should be negligible for this estimate. for lowest cost, select the smallest dpa-switch that has a minimum current limit that is at least 10% greater than the maximum primary current. the allowance of 10% greater current gives design margin with the ability to respond to transient loading. the second criterion for the selection is power dissipation. the smallest dpa-switch that will handle the current may dissipate too much power to meet the ef?ciency requirements. even if ef?ciency is not a concern, the smallest device may get too hot if system constraints prevent good thermal design. multiplication of the r ds(on) by the square of the rms current in the primary gives a reasonable estimate of the power dissipation in the dpa-switch . the dpa-switch dissipates approximately 25% of the total system loss in designs without synchronous recti?ers.
an-31 c 7/04 7 if power dissipation is a problem with the smallest device, select the next larger device and program the current limit with the x pin to 10% above the peak primary current. this is done to limit overload power capability. refer to the dpa-switch data sheet to determine the value of the resistor on the x pin that corresponds to the desired current limit. figure 3 illustrates how the ef?ciency is related to the selection of the dpa-switch . devices with lower r ds(on) dissipate less power where resistive voltage drop dominates the loss. thus, the ef?ciency is higher for larger devices at low input voltage. at higher input voltages the rms current in the dpa-switch decreases and the loss from capacitance on the drain increases, so the lower r ds(on) has virtually no effect on ef?ciency. clamp circuit all applications must protect the dpa-switch from excessive drain voltage. figure 1 shows a simple and effective solution. a zener diode from the drain to source provides a hard clamp. the 30 w prototype example (table 1), uses a 150 v zener to guarantee substantial margin from the breakdown voltage of 220 v. a small capacitor across the primary of the transformer may be necessary in conjunction with the zener clamp (see figure 4). the designer should put a placeholder for this capacitor on the initial prototype. in some designs there is suf?cient stray capacitance on the primary of the transformer to remove the need for this clamp capacitor. bench tests will determine whether the capacitor is required to maintain safe drain-to- source voltages. in normal steady-state operation, the capacitor c cp across the primary of the transformer absorbs energy from leakage inductance to keep the drain-to-source voltage below the zener voltage. there is an optimum value for c cp that typically ranges between 10 pf and 100 pf for converters in the range of 10 w to 40 w. the value of c cp depends on the leakage inductance and the peak current. the proper value of capacitance will allow most of the energy in the leakage inductance to be recovered during the next switching cycle. too little capacitance will cause the zener diode to conduct. dissipation in the zener will reduce ef?ciency. too much capacitance will also reduce ef?ciency because it will increase turn-on losses in the dpa-switch and may also interfere with the reset of the transformer. the zener diode does not conduct during normal steady-state operation, but it is required to limit the drain voltage during start-up, transient loading and overload conditions. at higher powers, the clamp capacitor value (c cp ), becomes a limiting factor on the ef?ciency of the power supply. different techniques can be used for these higher power applications (above approximately 40 w). figures 5 and 6 show a non- dissipative clamp technique that also resets the transformer. see references [4] and [5] for a description of this technique. transformer reset circuit the ?ux in the magnetizing inductance of the transformer must be reset in each switching cycle to maintain volt-seconds pi-2875-062204 d s c control control vr1 c s r s dc input dc input dp a-switch u1 c cp + pi-3474-032603 d s control control dp a-switch dc input v oltage d2 l1 d1 c1 v 1 v ds + figure 4. components of the transformer clamp and reset circuit. figure 4. lc (inductor capacitor) reset and clamp.
an-31 c 7/04 8 balance and prevent saturation. since real transformers have ?nite inductance, they store parasitic energy that is represented as a magnetizing current. the magnetizing inductance cannot store very much energy before it saturates. since a saturated transformer behaves like a short circuit, external circuitry must manage the removal of the energy from the magnetization inductance (reset the transformer) on each switching cycle. this transformer reset will require the voltage on the drain pin to rise above the input voltage. the designer needs to be sure that the transformer reset does not cause voltage overstress on the drain pin of the dpa-switch . figure 4 shows the components for the circuit that resets the magnetizing energy in the transformer to a safe value at the end of each switching cycle. the heart of the circuit is the series rc network (r s and c s ) that is connected across the output recti?er. when the dpa-switch turns off, current in the magnetizing inductance leaves the transformer through the secondary winding. the capacitor charges as the magnetizing current reduces to zero. the capacitor must be small enough to allow the magnetizing current to go to zero within the minimum offtime. an additional restriction on the size of the capacitor is that it must be large enough to keep the drain-to-source voltage below the voltage of the zener clamp under normal operating conditions. the resistor in the reset network damps oscillations from the interaction of the capacitor with parasitic inductance. the value of the resistor is typically between 1 ? and 5 ? . a different reset circuit is required for applications higher than about 40 w. figure 6 shows an example of a 70 w converter that uses the circuit of figure 5 to reset the transformer and to limit the voltage on the dpa-switch . veri?cation of transformer reset users should con?rm that the transformer resets under worst case conditions at the lowest and highest input voltages with measurements on the bench. figure 7 illustrates three situations that show proper transformer reset with the reset circuit in figure 4. three examples of improper transformer reset are shown in figure 8. the best way to assess the reset characteristics is to observe the drain-to-source voltage on the dpa-switch . figure 7 (a) shows the voltage on the prototype example when it operates from an input of 72 vdc. it is operating at full load with a reset capacitor (c s ) of 2.2 nf across the output recti?er. the clamp capacitor on the primary is 47 pf. see design idea di-24 (available on www.powerint.com ) for a circuit example. the ?gure shows the important intervals of the waveform within one switching period t s . dpa-switch is conducting during the time t on = d t s , where d is the duty ratio. flux in u1 dpa426r d4 42ct030s 1 9, 10 6, 7 3 2 c8 470 pf 200 v c10 220 nf c1 1 f 100 v c2 1 f 100 v c11 68 f 10 v c7 1 nf 1.5 kv r6 6.8 ? c12 4.7 nf 50 v r3 6.8 k ? 1 % r1 619 k ? r4 1.0 ? c18 100 f 10 v c19 100 f 10 v c20 1 f 10 v j1- 2 input rtn j1- 1 rtn +v in 36-72 vdc j1- 1 l1 1 h 2.5 a d l s x f c control control u2 pc357n3t dp a-switch t1 r5 6.8 ? d1 uf4003 d2 uf4003 l2 100 h c9 4.7 f 25 v bav19 ws d3 d5 42ct030s l3 3.3 h 20 a 5 v, 14 a j2- 2 l4 100 nh 20 a vr1 smbj 150 pi-2882-062204 c3, c4, c5, c6 1 f, 100 v (x4) c13, c14, c15, c16, c17 100 f, 10 v (x5) u2 d5 bav19ws u3 lm431aim3 r9 220 ? r11 5.1 ? r8 10 k ? c22 1 f c21 10 f 10 v c23 68 nf r10 220 ? r13 10.0 k ? 1% r14 10.0 k ? 1% figure 6. a 70 w dc-dc converter that uses an alternative circuit to reset the transformer.
an-31 c 7/04 9 pi-2884-061002 0 2.5 5 0 150 100 200 50 time ( s) voltage (v) voltage (v) voltage (v) 250 300 -50 -100 0 2.5 5 0 150 100 200 50 time ( s) 250 300 -50 -100 0 2.5 5 0 150 100 200 50 time ( s) 250 300 -50 -100 (a) (b) (c) t s t on t rz t rn t v0 0 2.5 5 0 150 100 200 50 time ( s) 250 30 0 -50 -100 0 2.5 5 0 150 100 200 50 time ( s) 250 30 0 -50 -100 pi-2885-061002 0 2.5 5 0 150 100 200 50 time ( s) 250 30 0 -50 -100 (a) (b) (c) voltage (v) voltage (v) voltage (v) figure 7. normal dpa-switch drain waveforms showing correct transformer reset. a) v in = 72 v, b) v in = 48 v, c) v in = 36 v. figure 8. illustration of three situations with improper transformer reset. a) v in = 72 v, b) v in = 36 v, c) v in = 36 v.
an-31 c 7/04 10 the transformer increases in the positive direction during t on , and resets to zero during the interval t rz . all the energy stored in the magnetizing inductance is removed during t rz to charge the reset capacitor and the clamp capacitor to maximum voltage. the ?ux increases in the negative direction during the interval t rn as the reset capacitor and the clamp capacitor discharge into the magnetizing inductance. the ?ux remains a constant negative value during the interval t v0 , where the voltage on the transformer windings is zero. it is easy to see that the primary voltage is zero during t v0 because the drain voltage is the same as the input of 72 v. the negative magnetizing current circulates in the secondary winding during t v0 . figure 7(b) shows the drain voltage on the same circuit when it operates at the nominal input of 48 vdc. the larger duty ratio is consistent with the lower input voltage. note that the intervals t rz and t rn are the same as at 72 v input, but now t v0 is nearly zero. figure 7(c) shows the situation at input voltage of 36 vdc, with a corresponding larger duty ratio. the transformer has reset to zero ?ux because the drain voltage has reached its peak during the interval t rz . the drain voltage is in the region of negative ?ux when the dpa-switch turns on. peak drain voltage under normal operating conditions should be less than 150 v. this includes peaks in the drain voltage from the reset of both leakage inductance and magnetizing inductance. figure 8 shows three cases of improper transformer reset. the prototype example has been modi?ed to create these illustrations. the rc network has been removed from the output recti?er to obtain the waveform in figure 8(a). the clamp capacitor c cp on the primary is 47 pf. the magnetizing energy resets into only the clamp capacitor and other stray capacitance. consequently, at 72 v input the drain voltage goes higher than desired. the ?gure shows the maximum drain voltage at 152 v, in contrast to 140 v in figure 7(a) with a proper reset network. the zener clamp voltage of 150 v is speci?ed at a current of 1 ma. although the zener clamp just barely conducts at 152 v, there is not suf?cient margin in this design to tolerate a transformer with lower primary inductance. figure 8(b) illustrates the situation of too much capacitance. the rc reset network has been restored with a proper capacitance of 2.2 nf, but c cp is increased to 470 pf, ten times the original value. the waveform shows operation at 36 vdc input and full load. the ?ux in the transformer has just barely reset to zero, as the dpa-switch turns on at the end of the t rz interval. a larger magnetizing inductance or a lower input voltage would not allow the transformer to reset. the final example of an improper transformer reset is figure 8(c). primary clamp capacitor c cp is restored to its original value of 47 pf, but the reset capacitor is increased to 47 nf. the converter is operating at 36 vdc. the drain voltage shows clearly that the transformer is not resetting completely. the dpa-switch turns on within the interval t rz . the ?ux in the transformer has not returned to zero. a small change in operating conditions could cause the transformer to saturate on every cycle or to run so close to saturation that it could not accommodate change in duty ratio from a load step. output capacitors the ripple current in the output inductor generates a voltage ripple on the output capacitors. part of the ripple voltage comes from the integration of the current by the capacitance, and part comes from the voltage that appears across the capacitor?s equivalent series resistance (esr). the capacitor must be selected such that the capacitance is high enough and the esr is low enough to give acceptable voltage ripple with the chosen output inductor. usually most of the ripple voltage comes from the esr. ripple voltage that is dominated by esr has a triangular waveform like the ripple current in the inductor. ripple voltage that is dominated by the capacitance has a waveform with segments that are parabolic instead of linear. output capacitors in dc-dc converters are typically solid tantalum. they are a good choice because of their low esr and low impedance at the frequencies used in these converters. the esr is also an important element in the design of the feedback loop. in this regard, a moderate amount of esr is desirable. the section on feedback design elaborates on the values of the components in the feedback circuit. it is important for designers to know that the value of esr may change signi?cantly over the speci?ed temperature range. the output ripple and the stability of the control loop can be affected by the change in esr. it is necessary to evaluate prototype hardware at the extremes of temperature to con?rm satisfactory performance. the voltage rating for the capacitors is typically 25% higher than the maximum operating voltage for reliability. the derating factor is thus 80%. for example, a 5 v output would have a capacitor that is rated for either 6.3 v or 10 v. the lower voltage capacitor would be smaller, whereas the higher voltage capacitor would have a lower failure rate in the application. feedback design stability is an important consideration for a switching power supply. three parameters that describe the characteristics of the control loop are crossover frequency, phase margin and gain margin. the crossover frequency is the frequency where the magnitude of the loop gain passes through 0 db. it is a measure of the system?s bandwidth.
an-31 c 7/04 11 u1 u2 d s c output output return r6 l2 r12 r10 c10 r11 c14 r9 r4 c5 u3 tl431 c6 c11 c16 pi-2876-062204 control control dp a-switch input return + figure 9. essential components of the feedback circuit. the schematic does not show esr of the output capacitors (component designators are the same as in the ep-21 prototype). the phase margin is speci?ed at the crossover frequency. it is the difference between the phase of the loop gain and 180 degrees. a stringent speci?cation will call for a phase margin of at least 60 degrees under worst case conditions. in no case should the phase margin be less than 45 degrees. this means the phase would have to decrease by that amount for the system to become unstable. phase margin is also related to the dynamic characteristics of the system. a low phase margin suggests an oscillatory response to a load step or other disturbance. it is also important that the loop gain decrease in magnitude beyond the crossover frequency. this requirement is generally speci?ed as gain margin. gain margin is the difference between 0 db and the magnitude of the loop gain at the frequency where the phase is 180 degrees. an acceptable gain margin is greater than 10 db. this means the magnitude would have to increase by that amount for the system to become unstable. loop gain should be measured at worst case conditions (generally maximum input voltage with maximum load) and at the extremes of the speci?ed ambient temperature, since important component parameters (especially capacitor esr) can change greatly with temperature. stabilizing a high frequency forward dc-dc converter presents some challenges due to the inherently high bandwidth of this topology. many dc-dc converter designs use cycle-by-cycle current-mode control. the dpa-switch uses classic voltage mode control to allow operation at duty ratios greater than 50% without the need for the stabilizing ramp (slope compensation) required with current-mode control. the fundamental system characteristics of the forward converter in continuous conduction mode with voltage mode control call for a compensation circuit with multiple poles and zeros to achieve the desired loop response. the crossover frequency for a control loop that uses dpa-switch in a forward converter with an optocoupler should be limited to 10 khz or less at maximum input voltage and room temperature. the dpa-switch has one internal pole at approximately 30 khz to ?lter switching noise. other poles at higher frequencies contribute additional phase shift at 30 khz. the optocoupler has two poles at approximately 100 khz. the phase shift from these poles, combined with the phase shift introduced by the lc ?lter at the output of the converter, is dif?cult to compensate above 10 khz. the objective of the feedback design is to reduce the magnitude of the loop gain to zero db at a frequency of 10 khz or less with a phase margin near 60 degrees. although system requirements and the dpa-switch ?x some quantities that determine loop characteristics, the designer can manipulate many components in the feedback circuit to optimize loop stability. figure 8 shows the essential components of a feedback circuit that uses an ordinary tl431 regulator to achieve the high loop gain
an-31 c 7/04 12 required for tight dc voltage regulation. not shown in the circuit diagram is the esr of the output capacitors. the esr is also an important element in the frequency compensation of the feedback loop. output lc filter the ?lter formed by the output inductor and the output capacitors contributes two poles to the loop response at the ?lter?s resonant frequency. since the ?lter is a resonant circuit with relatively low loss, the gain and phase change rather abruptly near the resonant frequency. consequently, the poles and zeros for shaping the loop response should either avoid this region or compensate for the resonance. proper placement of the resonant frequency of the output ?lter will avoid complications in the design of the feedback loop. the position of the resonant frequency should allow the designer to shape the desired response with a limited number of compensation components of reasonable size. the recommended resonant frequency for an output ?lter that uses low esr tantalum capacitors in a forward converter with dpa-switch and optocoupler feedback is between 4 khz and 6 khz. this value is consistent with the inductor and capacitor values for desirable ripple current and ripple voltage. 0.1 1 1 0 100 1 k 10 k 50 60 40 30 20 10 0 -10 -20 -30 -40 -50 -60 100 k 270 240 210 180 150 120 90 60 30 0 -30 -60 -90 pi-2878-032603 180 degrees phase 0 degrees phase margin phase margin 60 degrees z1 gain margin 20 db 0 degrees phase 180 degrees phase margin 56 db loop gain 0 db gain 1-gain 1-phase p1 p2 p3 p4 p6 z2 z3 z4 frequency (hz) gain (db) phase margin (degrees) p5 figure 10. gain and phase of a typical feedback loop for dc-dc forward converter with dpa-switch. markers show locations of major poles and zeros. the output capacitor esr contributes a zero that compensates for one of the poles from the ?lter. however, for low esr tantalum or organic electrolyte capacitors, this zero usually occurs too high in frequency to substantially offset the effects of the ?lter within the desired loop bandwidth. in the prototype example, the output ?lter capacitors are 100 f, with a maximum speci?ed esr of 100 milliohms. the esr zero is thus at approximately 16 khz, well beyond the 4 khz lc ?lter resonant frequency. actual esr is approximately 80 milliohms, placing the zero typically at 20 khz. in situations where standard low esr electrolytic capacitors can be used, the higher esr may place the esr zero at a suf?ciently low frequency to add signi?cant additional phase margin. dpa-switch compensation the network of c6 and r4 at the control pin of dpa-switch provides compensation for the feedback loop in addition to other functions. the capacitance of c6 with r4 and its own esr plus the impedance of the control pin impedance provide a pole in the loop gain, followed by a zero from r4 and the esr of c6. suggested values of c6 are between 47 f and 100 f. this range of values will generally be suf?cient to provide desirable
an-31 c 7/04 13 adjustments to the loop gain and to allow the capacitor to perform its other functions in the system. the zero introduced by r4 and the esr of c6 should be at approximately 25% of the output ?lter resonant frequency. this placement allows maximum gain reduction while minimizing the phase lag introduced by this network at the resonant frequency. in the prototype example, c6 is 68 f with an esr of about 1.6 ? . the impedance at the control pin of dpa-switch is typically 15 ? . these values put the pole at approximately 130 hz and the zero at approximately 900 hz. high frequency bypass capacitor c5 is small enough to have a negligible effect on the loop gain. optocoupler compensation the current transfer ratio (ctr) of the optocoupler is a major contributor to the magnitude of the loop gain near the crossover frequency. equally important is the resistor r6 in series with the optocoupler led. selection for either of these elements is not arbitrary, as the optocoupler provides power to the dpa-switch during normal operation. the combination of optocoupler and series resistor must deliver the maximum speci?ed control pin current for the dpa-switch at minimum speci?ed ctr. in most cases, an optocoupler with a ctr between 100% and 200% will suf?ce. the designer then selects r6 to provide the led current required at minimum ctr with a saturated tl431. the network of r12 and c16 in parallel with r6 creates a zero that boosts the gain and phase to compensate one of the poles from the output ?lter. the position of the zero is generally determined empirically to achieve the desired phase margin. it is typically set at a frequency between one and three times the resonant frequency of the output ?lter. resistor r12 limits the boost in gain at high frequencies. tl431 compensation the purpose of the tl431 is to provide high loop gain at low frequencies. its contribution is not necessary at higher frequencies where the optocoupler provides adequate gain. therefore, the feedback circuit has compensation around the tl431 to maximize its contribution at very low frequencies and to remove its in?uence at higher frequencies. the connection of c14 and r9 between the cathode and the reference terminal of the tl431 allows maximum loop gain at dc for the best voltage regulation. in the prototype example, capacitor c14 forms an integrator that reduces the contribution of the tl431 by 20 db per decade. resistor r9 with r10 sets the minimum gain from the tl431 and introduces a zero in the loop gain. the zero in the prototype example is at about 16 hz. another zero, local to the tl431, is formed by c14 and r9 at about 720 hz. the location of this zero is not critical for normal operation in continuous conduction mode, and does not appear in the loop gain of this example. it becomes important at very light loads where the converter operates in discontinuous conduction mode. the loop gain characteristic for discontinuous conduction mode is fundamentally different from this example of continuous conduction mode. the most signi?cant effect is that the loop gain will generally have a much lower crossover frequency that depends on the load. the crossover frequency could easily fall into the region where the tl431 contributes signi?cantly to the loop gain. loop gain of prototype circuit figure 10 shows the magnitude and phase of the loop gain of the prototype circuit for an input voltage of 72 v at a load current of 5 a. the highest input voltage is typically the worst case in forward converters because that is the condition for highest gain, yielding the highest bandwidth and lowest phase margin. the upper curve in figure 10 is the magnitude of the loop gain in units of db. the lower curve is the phase in units of degrees, with the scale shifted by 180 degrees to give the phase margin directly. the markers z1 through z4 and p1 through p6 show respectively the frequencies of the signi?cant zeroes and poles. the integrator formed by c14, r9 and r10 reduces the gain from its dc value such that the tl431 makes essentially no contribution to the gain at frequencies higher than z1. the asymptotes of the dc value and the 20 db per decade slope of the integrator create the pole at p1. gain is reduced by the pole at p2 that is formed by capacitor c6 with its esr, resistor r4, and the internal impedance of the control pin of the dpa-switch . the phase receives a boost from the zero formed by c6 and r4 with the esr of c6 at z2. the resistor r4 augments the esr of the capacitor. use a tantalum capacitor for c6 so that the total resistance can be adjusted by r4. the esr of an aluminum capacitor will generally be too large to allow the desired shaping of the frequency response. capacitor c5 provides a low impedance source for pulses of current into the control pin. its effect on the control loop is minor, appearing at p6, well beyond the 0 db crossover frequency. the zero at z2 provides partial cancellation of the pair of poles p3, p4 that originate from the output inductor and output capacitors of the forward converter. the network of c16, r6 and r12 gives additional cancellation with a zero at z3. the esr of the output capacitors gives a ?nal zero at z4. the internal high frequency ?lter of the dpa-switch provides the pole at p5.
an-31 c 7/04 14 the magnitude of the gain at frequencies greater than z1 is related directly to the current transfer ratio (ctr) of the optocoupler. therefore, the ctr must be controlled to maintain a stable and well-behaved system. designers should choose an optocoupler that has a ctr in the range of 100% to 200% at the maximum control pin current of 12 ma. the phototransistor of the optocoupler must also have a breakdown voltage greater than the maximum bias voltage. figure 10 shows that this example has a desirable phase margin of 60 degrees and a comfortable gain margin of 20 db. suf?cient margin is required in the design of the feedback loop to allow for tolerances in the ctr of the optocoupler, changes in esr of the output capacitor, and the change in gain with operating voltage. the esr can change signi?cantly with temperature. this should be a primary consideration in the selection of output capacitors. the design must also allow for tolerance variations in all other components. operation at no load those who design or specify dc-dc converters should pay particular attention to requirements for minimum load. the control characteristics are different for operation in the continuous conduction mode (moderate to heavy loads) and discontinuous conduction mode (light loads). the boundary between the two modes occurs at the load where k ? i = 2 (without synchronous recti?cation). u1 dpa425r d1 bav 19ws d2 c5 220 nf vr1 smbj 150 c6 68 f 10 v c7 1 nf 1.5 kv r14 10 ? t1 r3 18.2 k ? 1% r1 619 k ? 1% r4 1.0 ? c10 100 f 10 v c11 100 f 10 v c12 1 f 10 v 36-75 vdc l1 1 h 2.5 a l2 c1, c2 & c3 1 f 100 v d l s x f c control control u2 pc357n1t pi-3472-04090 3 dp a-switch 5 v, 6 a rtn q2 si4888 dy r15 10 ? r16 10 k ? d4 bav19ws r17 10 ? q1 si4888 dy c4 4.7 f 20 v u2 d3 bav19ws u3 lm431aim 3 r9 220 ? r11 10.0 k ? 1% r10 10.0 k ? 1% r12 5.1 ? r7 10 k ? c14 1 f c13 10 f 10 v c16 100 nf r6 150 ? v in + v in c17 3300 pf figure 11. example of dpa-switch in a single-ended dc-dc forward converter with synchronous recti?cation. the two modes have different control characteristics. the converter in discontinuous conduction mode will usually have a slower response to transients and higher ripple voltage at the output than in continuous conduction mode. in extreme cases, a converter that is well-behaved in continuous conduction mode may actually become unstable at light load or with no load unless correctly designed. many commercial dc-dc converter modules specify a large minimum load to prevent operation in discontinuous conduction mode. a converter that operates deeply in discontinuous conduction mode requires a very small duty ratio. operation at very light loads is not a problem for dpa-switch because it automatically reduces the effective switching frequency by skipping cycles to give duty ratios less than about 5%. operation at small duty ratios requires a larger capacitor to keep the bias voltage above its minimum required value of 8 v. in a trade-off with size, cost and ef?ciency, the best solution to a requirement to operate with no load is to include a small preload in parallel with the output capacitors. the amount of the load is determined empirically to supplement the natural loading from the other small-signal circuits that get their power from the output. synchronous recti?cation the use of synchronous recti?cation can yield a substantial increase in ef?ciency over passive schottky recti?ers on the
an-31 c 7/04 15 q1 q2 d3 d4 r15 r16 c17 l2 pi-3475-062204 q1 q2 d3 r15 l2 pi-2989-062204 (a) (b) output voltage ef?ciency gain over diode recti?cation 5 v +3% 3.3 v +6% 2.5 v +8% figure 12. synchronous recti?cation (a) winding driven dc coupled. (b) winding driven ac coupled. table 3. ef?ciency gain vs. output voltage for synchronous recti?cation. output. for a 5 v output, an ef?ciency of 85% with schottky recti?ers would typically go to 90% or higher with synchronous recti?ers. synchronous recti?cation gives the bene?t of greater ef?ciency at lower output voltages as shown in table 3. dpa-switch has features that can simplify the design of synchronous recti?er circuits that are in common use. circuits for synchronous recti?cation with dpa-switch fall into three categories of increasing complexity. a) winding driven dc coupled b) winding driven ac coupled c) actively driven the ?rst two are shown in figures 11 and 12. mosfets q1 and q2 conduct at appropriate times to reduce the voltage drops associated with the output recti?ers of a forward converter. q2 performs the function of the forward recti?er. q1 operates as the catch recti?er with a parallel schottky diode. the voltage drop of each synchronous recti?er is dominated by the on-resistance of the mosfets multiplied by the rms load current, rather than by the average current times the minimum voltage of a schottky barrier. winding driven dc coupled synchronous recti?er the simplest way to drive synchronous rectifiers with dpa-switch is shown in figure 12 (a). the gate-to-source voltage that turns on the mosfets is essentially the voltage at the secondary winding of the transformer. the channel of the mosfet will conduct as long as the gate-to-source voltage exceeds the threshold voltage. the forward rectifier mosfet q2 turns on when the dpa-switch turns on to apply the dc input voltage across the primary winding. the direction of current in q2 is from source to drain. when the dpa-switch turns off, the reset voltage on the transformer forces a negative gate-to-source voltage on q2 and a positive gate-to-source voltage on q1. schottky diode d3 conducts until the gate-to-source voltage on q1 rises suf?ciently to exceed the threshold voltage. suitable mosfets for this application have threshold voltages typically between 4 v and 5 v. the permissible maximum gate- to-source voltage is usually 15 v to 20 v. these restrictions limit the range of input voltage for converter operation. the integrated line overvoltage feature of dpa-switch simpli?es the design of winding driven synchronous recti?ers. in most cases it eliminates the need for zener diodes to protect the gates of the mosfets from excessive voltage. excess voltage will not appear on the secondary of the transformer because the dpa-switch will not operate when the input voltage is too high. dc coupling of the gates in this con?guration permits a mode of operation that may not be desirable in some applications. during shutdown, the voltage across the output inductor will go to zero after its current decays to zero. the remaining output voltage will then appear across q1 and d3. if the output voltage is high enough (above the gate threshold of q2) it will turn on q2, allowing reverse current to ?ow through l2 and the transformer secondary. the voltage on the secondary winding will saturate the transformer, abruptly turning off q2 and generating a voltage spike on the gate of q1. this voltage spike may exceed the rated gate voltage for q1. this behavior can occur in any design using this form of synchronous recti?cation with an undervoltage lockout. it is not speci?c to dpa-switch . a solution to this issue is offered below. winding driven ac coupled synchronous recti?er the ac coupled circuit of figure 12 (b) eliminates the high voltage spike by limiting the on-time of q2 such that signi?cant reverse current cannot ?ow through l2 and the secondary
an-31 c 7/04 16 winding. capacitor c17 should be chosen to capacitively divide the winding voltage between c17 and the c gs of mosfet q2, to provide a voltage on c gs that exceeds the q2 threshold voltage. the time constant of c17 and r16 should be about 10 s for 300 khz operation. r15 is typically about 10 ? . figure 11 shows the dpa-switch in a single-ended dc-dc forward converter that uses winding driven ac coupled synchronous recti?cation. in this example, the gate of q1 has enough capacitance to eliminate the need for the discrete capacitor c s in the transformer reset circuit. although this is often the case with synchronous recti?ers that are winding driven, designers should follow the guidance in the section on veri?cation of transformer reset to con?rm that the transformer resets properly. actively driven synchronous recti?ers the third category of synchronous recti?er circuits uses independent active components that may include discrete devices and integrated circuits to lock onto the switching frequency of the power supply and to drive the mosfets. this solution relaxes the restriction on the range of input voltage because the driver can regulate the gate voltage to be independent of the voltage on the secondary winding. circuits for actively driven synchronous recti?ers are much more complex than the other solutions, and are beyond the scope of this application note. table 4 gives a comparison of the techniques for synchronous recti?cation. in general, dpa-switch with synchronous recti?ers should operate at the lower switching frequency of 300 khz. the synchronous recti?er catch mosfets typically have gate- source capacitance values such that the transformer would have insuf?cient time to reset at 400 khz. connect the f pin to the control pin to select the lower switching frequency. layout considerations figure 13 shows an example of a proper circuit board layout for a forward converter with dpa-switch . since the dpa-switch can operate with large drain current, designers should follow these guidelines carefully. primary side connections the tab of dpa-switch is the intended return connection for the high switching currents. therefore, the tab should be connected by wide, low impedance traces to the input capacitor. the source pin should not be used to return the power currents; incorrect operation of the device may result. the source pin is intended as a signal ground only. the device tab (source) is the correct connection for power currents. the bypass capacitor on the control pin should be located as close as possible to the source and control pins. the circuit trace of its connection to source should not contain any switching current from the primary or bias voltages. all source pin referenced components connected to the line-sense (l) or external current limit (x) pins should also be located closely between their respective pins and source. once again, the source connection trace of these components should not conduct any of the main mosfet switching currents. it is critical that tab (source) power switching currents are returned to the negative terminal of the input capacitor through a separate trace that is not shared by the components connected to the source, control, l or x pins. any traces to the l or x pins should be kept as short as possible and away from the drain trace to prevent noise coupling. line- sense resistor (r1 in figure 11) should be located close to the l pin to minimize the trace length on the l pin side. in addition to the control pin capacitor (c5 in figure 11), a 220 nf high frequency bypass capacitor in parallel is recommended as close as possible between source and control pins for better noise immunity. the feedback optocoupler output should also be located close to the control and source pins of dpa-switch . heat sinking to maximize heat sinking of the dpa-switch and the other power components, special thermally conductive pc board material (aluminum clad pc board) is recommended. this has an aluminum sheet bonded to the pc board during the manufacturing process to provide heat sinking directly or to allow the attachment of an external heat sink. if normal pc synchronous recti?er type ef?ciency complexity and cost comment winding driven dc coupled ? ? check gate voltage at power down winding driven ac coupled ? ? gate voltage controlled at power down active drive ? ??? high complexity table 4. comparison of synchronous recti?cation techniques.
an-31 c 7/04 17 v v pi-2883-060602 solder side component side top view s l c x transformer - + v + - dc out maximize hatched copper area for optimum heat sinking v via between board layers v opto- coupler inductor (coupled) output diode d dp a-switc h figure 13. layout considerations for dpa-switch using r package. board material is used (such as fr4), providing copper areas on both sides of the board and using thicker copper will improve heat sinking. if an aluminum clad board is used, then shielding of switching nodes is recommended. this consists of an area of copper placed directly underneath switching nodes such as the drain node and output diode to provide an electrostatic shield to prevent coupling to the aluminum substrate. these areas are connected to input negative in the case of the primary and output return for secondary. this reduces the amount of capacitive coupling into the insulated aluminum substrate that can then appear on the output as ripple and high frequency noise. quick design checklist as with any power supply design, all dpa-switch designs should be veri?ed on the bench to make sure that component speci?cations limits are not exceeded under worst case conditions. the following minimum set of tests for dpa-switch forward converters is strongly recommended: 1. maximum drain voltage C verify that peak drain-to-source voltage does not exceed minimum bv dss at highest input voltage and maximum overload output power. it is normal, however, to have additional margin of approximately 25 v below bv dss to allow for other power supply component unit-to-unit variations. maximum overload output power occurs when the output is loaded to a level just before the power supply goes into auto-restart (loss of regulation). 2. transformer reset margin C drain voltage should also be checked at highest input voltage with a severe load step (50% to 100%) to verify adequate transformer reset margin. this test slews the duty cycle at high input voltage, placing the most demand on the transformer reset circuit. 3. maximum drain current C at maximum ambient temperature, maximum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of transformer or output inductor saturation and excessive leading edge current spikes. dpa-switch has a leading edge blanking time of 100 ns to prevent premature termination of the cycle. verify that the leading edge current spike does not extend beyond the blanking period.
an-31 c 7/04 18 4. thermal check C at maximum output power, minimum input voltage and maximum ambient temperature, verify that temperature speci?cations are not exceeded for the transformer, output diodes, output inductors and output capacitors. the dpa-switch is fully protected against overtemperature conditions by its thermal shutdown feature. it is recommended that suf?cient heat sinking is provided to keep the tab temperature at or below 115 c under worst case continuous load conditions (at low input voltage, maximum ambient and full load). this provides adequate margin to minimum thermal shutdown temperature (130 c) to account for part-to-part r ds(on) variation. when monitoring tab temperature, note that the junction-to-case thermal resistance should be accounted for when estimating die temperature. design tools up-to-date information on design tools is available at the power integrations website: www.powerint.com . references [1] ferroxcube (formerly philips) core supplier C www.ferroxcube.com. [2] tdk cores supplier C www.component.tdk.com/ components/ ferrite.asp. [3] avx (thompson) core supplier - www.avxcorp.com. [4] m. domb, r. redl, and n.o. sokal. nondissipative turn-off snubber in a forward converter: analysis, design procedure, and experimental veri?cation, of?cial proceedings of the tenth international pci ?85 conference, pp. 54-68. [5] t. ninomiya, t. tanaka, and k. harada, analysis and optimization of a nondissipative lc turn-off snubber, ieee transactions on power electronics, vol. 3, no. 2, april 1988, pp. 147-156.
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an-31 c 7/04 20 for the latest updates, visit our web site: www.powerint.com power integrations may make changes to its products at any time. power integrations has no liability arising from your use of any information, device or circuit described herein nor does it convey any license under its patent rights or the rights of others. power integra tions makes no warranties herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including circuits external to the products and transformer construction) may be covered by one or more u.s. and foreign patents or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations? patents may be found at www.powerint.com. life support policy power integrations? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. life support devices or systems which, (a) are intended for sur gical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi? cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch , tinyswitch , linkswitch and ecosmart are registered trademarks of power integrations. pi expert and dpa-switch are trademarks of power integrations. ?copyright 2003, power integrations power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasalespowerint.com china (shanghai) rm 807, pacheer commercial centre 555 nanjing west road shanghai, 200041, china phone: +86-21-6215-5548 fax: +86-21-6215-2468 e-mail : chinasalespowerint.com china (shenzhen) room 2206-2207, block a, electronics science & technology bldg., 2070 shennan zhong road, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasalespowerint.com germany rueckertstrasse 3 d-80336, muenchen, germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosalespowerint.com india (technical support) innovatech 261/a, ground floor 7th main, 17th cross, sadashivanagar bangalore 560080 phone: +91-80-5113-8020 fax: +91-80-5113-8023 e-mail: indiasalespowerint.com italy via vittorio veneto 12, bresso milano, 20091, italy phone: +39-028-928-6001 fax: + 39-028-928-6009 e-mail: eurosalespowerint.com japan keihin-tatemono 1st bldg. 12-20 shin-yokohama 2-chome, kohoku-ku, yokohama-shi, kanagawa 222-0033, japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansalespowerint.com korea 8th floor, dongsung bldg. 17-8 yoido-dong, youngdeungpo-gu, seoul, 150-874, korea phone: +82-2-782-2840 fax: +82-2-782-4427 e-mail: koreasalespowerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesalespowerint.com taiwan 5f-1, no. 316, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansalespowerint.com uk (europe & africa headquarters) 1st floor, st. james?s house east street farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-140 fax: +44 (0) 1252-727-689 e-mail: eurosalespowerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date a 1) C 6/02 b 1) added new information: bias circuits and synchronous recti?cation. 4/03 c 1) minor error corrections in the text. 7/04

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